The integrated circuit industry has, since its inception, maintained a remarkable growth rate by driving increased device functionality at lower cost. Leading edge devices today provide the computing power of computers that used to occupy entire rooms at a mere fraction of the cost. Many of today's low cost consumer devices include functionality that only a few years ago was unavailable at any cost, such as video cell phones, ultra-portable media players, and wireless or ultra-wideband Internet devices. One of the primary enabling factors of this growth has been the ability of optical lithography processes to steadily decrease the smallest feature size that can be patterned as part of the integrated circuit pattern. This steady decline in feature size and cost while at the same time printing more features per circuit is commonly referred to as “Moore's Law” or the lithography “roadmap.”
The lithography process involves creating a master image on a mask, or reticle, then replicating that pattern faithfully onto the device wafers. The more times a master pattern is successfully replicated within the design specifications, the lower the cost per finished device or “chip.” Until recently, the mask pattern has been an exact duplicate of the desired pattern at the wafer level, with the exception that the mask level pattern may be several times larger than the wafer level pattern. This scale factor is then corrected during wafer exposure by the reduction ratio of the exposure tool. The mask pattern is typically formed by depositing and patterning a light absorbing material on a quartz or other transmissive substrate. The mask is then placed in an exposure tool known as a “stepper” or “scanner” where light of a specific exposure wavelength is directed through the mask onto the device wafers. The light is transmitted through the clear areas of the mask and attenuated by a desired amount, typically between 90% and 100%, in the areas that are covered by the absorbing layer. The light that passes through some regions of the mask may also be phase-shifted by a desired phase angle, typically an integer fraction of 180 degrees. After being collected by the exposure tool, the resulting aerial image pattern is then focused onto the device wafers. A light sensitive material deposited on the wafer surface interacts with the light to form the desired pattern on the wafer, and the pattern is then transferred into the underlying layers on the wafer to form functional electrical circuits according to well known processes.
In recent years, the feature sizes being patterned have become significantly smaller than the wavelength of light used to transfer the pattern. This trend towards “sub-wavelength lithography” has resulted in increasing difficulty in maintaining adequate process margins in the lithography process. The aerial images created by the mask and exposure tool lose contrast and sharpness as the ratio of feature size to wavelength decreases. This ratio is quantified by the k1 factor, defined as the numerical aperture of the exposure tool times the minimum feature size divided by the wavelength. The lack of sharpness or image blur can be quantified by the slope of the aerial image at the threshold for image formation in the resist, a metric known as “edge slope,” or “normalized image log slope,” often abbreviated as “NILS.” The smaller the NILS value, the more difficult it becomes to replicate the image faithfully onto a large number of device patterns with sufficient control to yield economically viable numbers of functional devices. The goal of successful “low-k1 lithography” processes is to maintain the highest NILS possible despite the decreasing k1 value, thereby enabling the manufacturability of the resulting process.
New methods to increase the NILS in low-k1 lithography have resulted in master patterns on the mask that are not exact copies of the final wafer level pattern. The mask pattern is often adjusted in terms of the size of the pattern as a function of pattern density or pitch. Other techniques involve the addition or subtraction of extra corners on the mask pattern (“serifs,” “hammerheads,” and other patterns), and even the addition of geometries that will not be replicated on the wafer. In order to enhance the printability of the intended features, these non-printing “assist features” may include scattering bars, holes, rings, checkerboards, or “zebra stripes” to change the background light intensity (“gray scaling”), and other structures, which are well documented in the literature. All of these methods are often referred to collectively as “Optical Proximity Correction,” or “OPC.”
The mask may also be altered by the addition of phase-shifting regions that may or may not be replicated on the wafer. A large variety of phase-shifting techniques has been described at length in the literature including alternate aperture shifters, double expose masking processes, multiple phase transitions, and attenuating phase-shifting masks. Masks formed by these methods are known as “Phase Shifting Masks,” or “PSMs.” All of these techniques to increase NILS at low-k1, including OPC, PSM, and others, are referred to collectively as “Resolution Enhancement Technologies,” or “RETs.” The result of all of these RETs, which are often applied to the mask in various combinations, is that the final pattern formed at the wafer level is no longer a simple replicate of the mask level pattern. In fact, it is becoming impossible to look at the mask pattern and simply determine what the final wafer pattern is supposed to look like. This greatly increases the difficulty in verifying that the design data is correct before the mask is made and wafers exposed, as well as verifying that the RETs have been applied correctly and that the mask meets its target specifications.
The cost of manufacturing advanced mask sets is steadily increasing. Currently, the cost has already exceeded one million dollars per mask set for an advanced device. In addition, the turn-around time is always a critical concern. As a result, computer simulations of the lithography process, which assist in reducing both the cost and turn-around time, have become an integral part of semiconductor manufacturing. There are a number of computer software techniques that address needs in lithography simulation. For example, there is first-principle-modeling-based simulation software that conducts detailed simulation of the physical and chemical processes. However, such software often runs extremely slow and hence is limited to extremely small areas of a chip design (on the order of a few square microns). Software tools in this category include “SOLID-C” from Sigma-C (Santa Clara, Calif., USA) and “Prolith” from KLA-Tencor (San Jose, Calif., USA). Although there is computer software that executes and provides simulation results faster, such software uses empirical models that are calibrated to the experimental data (for example, “Calibre” from Mentor-Graphics in Wilsonville, Oreg., USA). Even for the “fast” simulation that uses empirical models, a simulation at a full-chip level often requires tens of hours to many days. A new, fast, and accurate approach has been described in U.S. Pat. No. 7,003,758, entitled “System and Method for Lithography Simulation,” the subject matter of which is hereby incorporated by reference in its entirety, and is referred to herein as the “lithography simulation system.”
As illustrated schematically in FIG. 1A, a lithography simulation typically consists of several functional steps, and the design/simulation process resembles a linear flow 100. In step 110, a design layout that describes the shapes and sizes of patterns that correspond to functional elements of a semiconductor device, such as diffusion layers, metal traces, contacts, and gates of field-effect transistors, is created. These patterns represent the “design intent” of physical shapes and sizes that need be reproduced on a substrate by the lithography process in order to achieve certain electrical functionality and specifications of the final device.
As described above, numerous modifications to this design layout are required to create the patterns on the mask or reticle used to print the desired structures. In step 120, a variety of RET methods are applied to the design layout in order to approximate the design intent in the actually printed patterns. The resulting “post-RET” mask layout differs significantly from the “pre-RET” design layout created in step 110. Both the pre- and post-RET layouts may be provided to the simulation system in a polygon-based hierarchical data file in, e.g., the GDS or the OASIS format.
The actual mask will further differ from the geometrical, idealized, and polygon-based mask layout because of fundamental physical limitations as well as imperfections of the mask manufacturing process. These limitations and imperfections include, e.g., corner rounding due to finite spatial resolution of the mask writing tool, possible line-width biases or offsets, and proximity effects similar to the effects experienced in projection onto the wafer substrate. In step 130, the true physical properties of the mask may be approximated in a mask model to various degrees of complexity. Mask-type specific properties, such as attenuation, phase shifting design, etc., need be captured by the mask model. The lithography simulation system described in U.S. Pat. No. 7,003,758 may, e.g., utilize an image/pixel-based grayscale representation to describe the actual mask properties.
A central part of lithography simulation is the optical model, which simulates the projection and image forming process in the exposure tool. In step 140, an optical model is generated. The optical model needs to incorporate critical parameters of the illumination and projection system: numerical aperture and partial coherence settings, illumination wavelength, illuminator source shape, and possibly imperfections of the system such as optical aberrations or flare. The projection system and various optical effects, e.g., high-NA diffraction, scalar or vector, polarization, and thin-film multiple reflection, may be modeled by transmission cross coefficients (TCCs). The TCCs may be decomposed into convolution kernels, using an eigen-series expansion. For computation speed, the series is usually truncated based on the ranking of eigen-values, resulting in a finite set of kernels. The more kernels are kept, the less error is introduced by the truncation. The lithography simulation system described in U.S. Pat. No. 7,003,758 allows for optical simulations using a very large number of convolution kernels without negative impact on computation time and therefore enables highly accurate optical modeling. See “Optimized Hardware and Software for Fast, Full Chip Simulation,” Y. Cao et al., Proc. SPIE Vol. 5754, 407 (2005). While here the mask model generated in step 130 and the optical model generated in step 140 are considered to be separate models, the mask model may conceptually also be considered as part of an integrated optical model.
Further, in order to predict shapes and sizes of structures formed on a substrate, in step 160 a resist model is used to simulate the effect of projection light interacting with the photosensitive resist layer and the subsequent post-exposure bake (PEB) and development process. A distinction can be made between first-principle simulation approaches that attempt to predict three-dimensional resist structures by evaluating the three-dimensional light distribution in resist, as well as microscopic, physical, or chemical effects such as molecular diffusion and reaction within that layer. On the other hand, all “fast” simulation approaches that may allow full-chip simulation currently restrict themselves to more empirical resist models that employ as an input a two-dimensional aerial image provided by the optical model part of the simulator. This separation between the optical model and the resist model being coupled by an aerial image 150 is schematically indicated in FIG. 1A. For simplicity, here the fact that the resist model may be followed by modeling of further processes, e.g., etch, ion implantation, or similar steps, is omitted.
Finally, in step 170, the output of the simulation process will provide information on the predicted shapes and sizes of printed features on the wafer, such as predicted critical dimensions (CDs) and contours. Such predictions allow a quantitative evaluation of the lithographic printing process and on whether the process will produce the intended results.
In order to provide the predictive capabilities just mentioned, a number of fitting parameters that are not known a priori need be found or tuned in a calibration process. Various methods of calibrating lithography models have been described in the literature. Generally, these calibration methods search for the best overall match between simulated test patterns and corresponding test patterns that are printed on actual wafers and measured by a metrology tool, e.g., a CD-SEM or a scatterometry tool.
Accuracy and robustness of the calibration are required to predict CDs of printed patterns, edge placements, and line end placements. The calibrated model is in general expected to predict one-dimensional as well as two-dimensional optical and processing related proximity effects with sufficient accuracy. It is known that the predictability of empirical models is mostly limited to a pattern geometry space that has been covered by the shape and size variations of the test or gauge structures used in the calibration procedure. A current practice and trend is to include more and more test structure variations to cover as wide and dense a geometry space as practically possible. Typically, thousands of measurement points are utilized for model calibrations. However, currently model calibrations are mostly performed at nominal or “best” optical settings, and therefore only cover the two-dimensional geometry space. Extrapolating these models for use when any non-geometry parameters, e.g., optical parameters or lithography process parameters, are changed is difficult.
On the other hand, it is well known that lithographic processes generally need to be evaluated by their process window or, more precisely, by the common process window of all relevant structures. The size of the process window (PW) is commonly measured by an area in exposure-defocus (E-D) space over which variations in the CD or edge placement fall within an allowable range. See “The Exposure-Defocus Forest,” B. J. Lin, Jpn. J. Appl. Phys. 33, 6756 (1994). Process window analysis takes into account that any actual manufacturing process is subject to unavoidable variations of real parameter values, such as exposure dose and focus settings of the lithographic projection system. The common process window of all structures on a device design defines the process margin, i.e., the tolerance against process parameter variations.
Some recent attempts to predict the through-process window behavior of OPC models by calibrating the resist model at “best” settings and extrapolating towards variations in dose and defocus have not been very successful, unless separate, discrete model calibrations were performed at different defocus settings. See “High accuracy 65 nm OPC verification: full process window model vs. critical failure ORC,” A. Borjon et al., Proc. SPIE Vol. 5754, 1190 (2005). FIG. 1B illustrates multiple locations covering a process window space, where separate model calibrations were performed at each location. In other work, attempts were made to calibrate models to several focus-exposure-matrix data sets but only for one-dimensional line-width data. See “Do we need complex resist models for predictive simulation of lithographic process performance?,” B. Tollkühn et al., Proc. SPIE Vol. 5376, 983 (2004).
In addition, “lumped” parameter models exist, in which the response of the system with respect to resist development effects are approximated by artificially changing the optical model parameters and such models may still be able to be well-calibrated against a set of test patterns at one single process window condition. As another example for illustration, it is well-known that spherical aberration of a projection system causes a pattern-pitch dependent focus shift. Consequently, if measured at a single focus setting, a through-pitch “OPC” curve (which plots CD versus pitch) will experience a certain modulation due to the optical effect of spherical aberration. A sufficiently complex resist model having a large enough number of adjustable parameters may still be able to reproduce the OPC curve and in fact predict printed CD through pitch at the exact same focus setting that was used for calibration. However, the ability of the model to extrapolate anywhere outside the immediate parameter space covered by the calibration would be severely limited.
There is a constant need for increased accuracy and robustness of lithography modeling. Clearly there is also a need for model calibration methodologies that enable predictive modeling in a multidimensional parameter space, beyond geometry variations but also PW-related process variations, in order to verify manufacturability of advanced semiconductor designs by simulation.